Xilinx provides a PCI Express Gen3 Integrated block for PCI Express® (PCIe) in the UltraScale™ family of FPGAs. The UltraScale FPGA solution for PCI Express Gen3 includes all of the necessary components to create a complete solution for PCIe. Delivered through Vivado®, the Xilinx IP for Endpoint and Root Port simplifies the design process and reduces time-to-market.
This core combined with Xilinx Targeted Design Platforms, helps customers develop system solutions.
UltraScale Gen3 Integrated Block for PCI Express (PCIe)
Overview
Key Features
- High Peformance and High Bandwidth Applications
- Compute and Data Co-processing Applications
- Medical Imaging, High-Performance Computing & Communications Packet Processing
Technical Specifications
Related IPs
- Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
- UltraScale+ Device Integrated Block for PCI Express (PCIe)
- Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe)
- Virtex-6 Integrated Block for PCI Express (PCIe)
- 7 Series Gen2 Integrated Block for PCI Express (PCIe)
- 7 Series Integrated Block for PCI Express (PCIe)