Ultra-low power processor with RISC-V architecture possessing secure execution capability

Overview

Key Features

• Instruction set: T-Head ISA (compatible with RV32EMC/RV32EC/RV32IMC);
• Pipeline: 2-stage;
• Permission mode: Optional M state or M+U state;
• General register: 16 32-bit GPRs;
• Bus interface: Dual bus (instruction bus + data bus);
• Memory protection: 0 to 16 optional protection zones;
• Tight coupling IP: Interrupt controller and timer;
• Multiplier: Optional slow multiplier and fast multipliers.
• Secure execution technology: Resists any hardware and software attack, and increases system security;
• Low-power cache: Reduces system memory access latency, and improves memory efficiency;
• Dynamic adjustment of interrupt priority: Enhancing real-time system performance, and implementing interrupt priority inversion in specific scenarios;
• Single-cycle memory speculation execution: Makes full use of memory bandwidth, so that the processor is completely streamlined.

Block Diagram

Applications

• Wireless Connectivity;
• Industrial Control

Technical Specifications