The BA51 is a highly configurable, low-power, deeply embedded RISC-V processor IP core. It implements a single-issue, in-order, 2-stage execution pipeline and supports the RISC-V 32-bit base integer instruction set (RV32I), or the 32-bit base embedded instructions set (RV32E).
Configuration Options for Broad Application Support
The processor core can be configured to meet different application requirements. It can optionally support user and supervisor privilege modes, as well as the ISA extensions for Compressed Instructions (C), Integer Multiplication and /Division Instructions (M), Atomic Instructions (A), User-Level Interrupts (N), Control and Status Register (Zicsr), and Instruction-Fence (Zifencei). Support for the single-precision floating-point (F) ISA extension can also be added upon request. And code size reduction (Zc) ISA extensions can also be added upon request.
Furthermore, the BA51 supports software and timer interrupts and up to 64 external interrupt lines. It features a remarkably low interrupt response time, which makes the core ideal for real time control applications. The time elapsed from when an external interrupt is asserted until the first instruction in the resolved interrupt handler can be issued is just 4 clock cycles. The user can minimize the core’s silicon footprint by choosing not to implement internal modules such as the machine mode internal timers and counters; the vectored interrupt controller (VIC); or the debug, power management (PMU), or memory protection (MPU) units. Finer-grained controls give designers the means to further tune the processor’s features and size to their specific design needs, including the number and size of memory regions for the MPU, the mapping of memory addresses to interfaces, and the width of the instruction and data buses
The user can minimize the core’s silicon footprint by choosing not to implement internal modules such as the machine mode internal timers and counters; the vectored interrupt controller (VIC); or the debug, power management (PMU), or memory protection (MPU) units. Finer-grained controls give designers the means to further tune the processor’s features and size to their specific design needs, including the number and size of memory regions for the MPU, the mapping of memory addresses to interfaces, and the width of the instruction and data buses.
The processor can optionally be equipped with a highly configurable instruction cache. The set associativity of this L0 cache can be specified from 1 to 4, while its block size and total size are also configurable at synthesis time.
Compact & Energy Efficient
Designed for low energy consumption the BA51 is compact and enables advanced power management. Under its minimal configuration the processor size is just 16k gates, and even when most of the optional features are enabled, its size is about 50k gates. This small silicon footprint is critical for minimizing leakage currents during idle or standby modes and for reducing dynamic power consumption. The BA51 also enables dynamic clock gating, unused modules power shut-off, and software or hardware dynamic frequency scaling of the bus and the CPU.
Furthermore, delivering more processing power per MHz than most processors in its class, the BA51 can be configured to operate at low frequencies to further save power, or to meet the most demanding embedded processing requirements, or any optimum combination of both.
Easy Integration and Low Risk
The processor core uses AMBA®, AXI-4 and low-latency Quickaccess Memory (QMEM) interfaces for fetching instructions and accessing data and peripherals, while the debug unit connects to an external JTAG/TAP controller via an APB port. Part of the family of processor cores available from CAST for more than a decade and used by hundreds of customers, the BA51 IP core has been designed for easy reuse and integration, has been rigorously verified, and is LINT-clean, scan-ready and silicon-proven. It is available in Verilog source code for ASICs or FPGAs.
Part of the family of processor cores available from CAST for more than a decade and used by hundreds of customers, the BA51 IP core has been designed for easy reuse and integration, has been rigorously verified, and is LINT-clean, scan-ready and silicon- proven. It is available in Verilog source code for ASICs or FPGAs
