UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8

Overview

Arasan's Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices.

Mobile phones, UMPC, DSC, PMP are some of the typical applications for UFS Host Controller IP. Majority of these applications require mass storage and bootable storage memory with an option for an external card.

The IP incorporates the latest UFS Host Controller Interface (HCI) version 3.0. Arasan’s MIPI M-PHY® HS-G4 IP is available in GDSII format for a variety of process technologies and MIPI UniProSM version 1.8 link layer with support for multi-lane operation and the optional Unified Memory Architecture (UMA) implementation.

Arasan’s UFS 3.0 Host Controller allows for highly secured applications by employing AES encryption. The data encryption and decryption is done seamlessly by the controller as data is written to or read from the UFS 3.0 device.

Key Features

UFS 3.0 Host and Device configurations available
Complete UFS 3.0 hardware implementation
Interop-proven UniPro 1.8 link layer
MIPI M-PHY 4.0 Interface
High speed mode Gear 1, Gear 2 , Gear 3 and Gear 4.
Supports 2 lanes for 23.3 Gbps max bandwidth
Task management operations
Supports multiple partitions (LUNs) (to dummy memory) with partition management
Definable write-protect group size
Boot mode operation
Device enumeration and discovery
Background operations
Secure Erase and Trim operations enhance security
Supports Write-protect options
Built-in advanced encryption standard (AES) hardware engine to exchange private data to storage device.

128bit key support
AES-CBC operating mode support
Capable of back-to-back processing for the data units that fit into an even number of 64-bit input words

Benefits

Seamless integration from PHY to Software
Assured compliance across all components
Single point of support
Easiest acquisition process (one licensing source)
Lowest overall cost including cost of integration
Lowest risk for fast time to market

Deliverables

Synthesizable RMM compliant Verilog RTL code.
Easy-to-use comprehensive OVM/UVM based randomized test environment (Ref. Sec 8, UFS VIP).
Synthesis scripts
Technical documents
User guide

Technical Specifications

Availability

Now

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