UART with FIFOs, IrDA and Synchronous CPU Interface

Overview

Key Features

• Capable of running all existing 16450 and 16550a software
• Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
• In FIFO mode, transmitter and receiver are each buffered with up to 256 byte FIFO’s to reduce the number of interrupts presented to the CPU
• Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes
• Adds or strips standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• Programmable baud generator divides any input clock by 1 to (2**16 - 1) and generates the 16 x clock
• Modem control functions (CTSn, RTSn, DSRn, DTRn, and DCDn)
• Programmable Auto-CTSn and Auto-RTSn
• In Auto-CTSn mode, CTSn controls the transmitter
• In Auto-RTSn mode, the receiver FIFO contents and threshold control RTSn
• Serial Port has an optional Infrared Data Association (IrDA) data port
• Fully programmable serial interface characteristics:
  • 5, 6, 7, or 8 bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1, 1½, or 2 stop bit generation
  • Baud generation
• False start-bit detection
• Complete status register
• Internal diagnostic capabilities: loop-back controls for communications link fault isolation
• Full prioritized interrupt system controls
• Optional IrDA or AMBA™ APB or CoreConnect™ OCP Bus Interface

Block Diagram

Technical Specifications