UART Assertion IP provides an efficient and smart way to verify the UART designs quickly without a testbench. The SmartDV's UART Assertion IP is fully compliant with standard UART Specification and provides the following features.
UART Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
UART Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.