TSN Ethernet Switched Endpoint Controller

Overview

The TSN-SE implements a configurable controller meant to ease the implementation of switched endpoints for Time Sensitive Net-working (TSN) Ethernet networks. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci).

The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. With cut-through switching and minimal buffering even at the Ethernet MAC level, the TSN-SE features extremely low and deterministic ingress and egress latencies and simplifies the development of time-aware applications. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements, and provides the system with timing information (timestamps, alarms, etc.) that is typically required for the operation of a TSN network bridge or endpoint.

The TSN-SE uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via AXI-Streaming interfaces with 32-bit data buses. To further expedite and ease the implementation of customer applications, DMA engines providing access to the stream interfaces via a memory-mapped AXI4 master port, and software stacks supporting higher-layer protocols, such as IEEE 802.1Qcc, IEEE 802.1Qca and SNMP, are optionally available

The TSN-SE is designed with industry best practices and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.  
 

Key Features

  • TSN Ethernet Switched Endpoint
    • Two Ethernet ports & one host processor port
    • Suitable for daisy-chained networks such as rings
    • 10/100/1000 Mbps (10Gbps soon)
  • Low Latency & Flexible Switching
    • Low-latency Layer-2 Cut-Through Switching
    • Run-time switch configuration enables fast response to network changes
    • 802.1Q Tagged VLAN support
    • Port-based VLAN
    • Configurable VLAN-PCP to TSN-Queue Mapping (QoS by PCP)
    • Flexible VLAN and MAC forwarding & filtering
    • Configurable MAC lookup table for dynamic and static entries & automatic aging table
    • Untagged ports support
    • Port Statisitics
  • TSN Features
    • Ready for IEEE 802.1AS-2020 (requires light-weight software stack)
    • Traffic shaping per IEEE 802.1Qav & IEEE 802.1Qbv with eight TSN-Queues
    • Frame preemption per IEEE 802.1Qbu and IEEE 802.3br
    • Frame Replication and Elimination per IEEE 802.1CB and Per-Stream Filtering and Policing per IEEE 802.1Qci optionally implemented in hardware
    • Path Control and Reservation per IEEE 802.1Qca, and Enhancements to Stream Reservation Protocol per EEE 802.1Qcc optionally implemented in software
  • Easy System Integration
    • AMBA™/AXI4 SoC Interfaces
      • 32-bit APB control/status interface
      • 32-bit AXI4-Stream for packet data
      • Optional AXI4 DMA engine
    • MII, GMII or RGMII, and MDIO Ethernet PHY interface per port
    • Requires minimal host assistance for the PTP stack, or no assistance from the host processor when licensed pre-integrated with an embedded processor
    • Complete FPGA reference designs available

Block Diagram

TSN Ethernet Switched Endpoint Controller Block Diagram

Technical Specifications

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Semiconductor IP