TSN Ethernet Endpoint Controller

Overview

The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci).

The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. Requiring minimal software assistance for its initialization, it features extremely low and deterministic ingress and egress latencies and simplifies the development of time-aware applications. While operating autonomously, the TSN-EP provides the system with timing information (timestamps, alarms, etc.) that is typically required for the operation of a TSN network endpoint device. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements. 

The TSN-EP uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via 32-bit-wide AXI-Streaming buses. To further expedite and ease the implementation of customer applications, DMA engines providing access to the stream interfaces via a memory-mapped AXI4 master port, and software stacks supporting higher-layer protocols, such as IEEE 802.1Qcc, IEEE 802.1Qca and SNMP, are optionally available.

The TSN-EP is designed with industry best practices and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.  

Key Features

  • TSN Ethernet Endpoint 
    • One Ethernet port & one host processor port
    • Suitable for star-topology networks
    • 10/100/1000 Mbps (10+ Gbps soon)
  • Time Synchronization
    • Implements IEEE 802.1AS-2020 
    • Grandmaster or Slave functionality
    • Highly accurate synchronization. Accuracy is typically in the order of a few tens ns.
    • Provides the system with timestamps, periodic event triggers and alarms 
  • Traffic Shaping
    • Implements Traffic Scheduling as per IEEE 802.1Qav and IEEE 802.1Qbv
    • Implements Frame Preemption as per IEEE 802.1Qbu and IEEE 802.3br
    • Supports up to 8 traffic classes, as per VLAN (IEEE 802.1Q)
    • Enables bandwidth reservation and allocation per traffic class, and deterministic, low-latency, low-jitter communication for all traffic classes 
  • Optional TSN Protocols
    • Frame Replication and Elimination (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci) optionally implemented in hardware
    • Path Control and Reservation per IEEE 802.1Qca, and Enhancements to Stream Reservation Protocol per EEE 802.1Qcc are optionally implemented in software
  • Easy System Integration
    • AMBA/AXI4 Interfaces
      • 32-bit APB for control/status registers
      • 32-bit AXI4-Stream for packet data
      • Optional AXI4 DMA engine
    • MII, GMII and RGMIII Ethernet PHY interface
    • Requires minimal host assistance for its initialization
    • Complete FPGA reference designs available

Block Diagram

TSN Ethernet Endpoint Controller Block Diagram

Technical Specifications

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Semiconductor IP