TSMC CLN7FFLVT 7nm Deskew PLL - 600MHz-3000MHz

Overview

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.

Key Features

  • Designed to eliminate clock distribution latency in systems and individual chips.
  • Precisely aligns the clock distribution output with a reference clock.
  • Provides a zero-delay feedback divider and zero-skew divided clock outputs.

Deliverables

  • GDSII (100% DRC and LVS clean)
  • LVS Spice netlist
  • Verilog model
  • Synopsys synthesis model
  • LEF for clock generator PLL
  • User Guidelines including:
    • integration guidelines,
    • layout guidelines,
    • testability guidelines,
    • packaging guidelines,
    • board-level guidelines

Technical Specifications

Foundry, Node
TSMC CLN7FFLVT
TSMC
Pre-Silicon: 7nm
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Semiconductor IP