IGAD2DY02A is a GLink-3D high speed die-to-die interface Master PHY. It is used to transmit data between dies and assembled using TSMC System on Integrated Chips (SoIC) 3D stacking technology (3DFabric). The IP supports both Wafer-on-wafer (WoW) and Chip-on-wafer (CoW) assembly, with both face to face and face to back options. It is used to communicate with IGAD2DX03A (Slave PHY). Both IGAD2DY02A and IGAD2DX03A are built with TX and RX Data and Command Slices in a modular way. Each Data Slice allows transferring 16 bits at bit rate of 5.0 Gbps in one direction, totaling 80 Gbps per Data Slice.
The IP contains PMAD and PMAA modules. PMAA supports data transmission with DDR interface on data/address slice and SDR interface on command slice. PMAD provides parity generation and checker plus lane repair functions. PMAD also provides full Scan support, Loopback, BIST generator and checker plus data training with IGAD2DX03A (Slave PHY).
TSMC CLN5FF GLink-3D Die-to-Die Master PHY
Overview
Key Features
- Supports SoIC (3DFabric) CoW and WoW assembly
- Supports face to face and face to back with the same GDSII
- Supports point to multi-point (multi-Slave) communication
- Up to 5 Gbps/bond (2.5 GHz DDR) data rate
- 16 TX/RX lanes/data slice and 16 TX lanes/address slice (DDR)
- 14 TX lanes/command slice (SDR)
- Supports 4 TX and 4 RX data slices, 2 address slices and 1 command slice
- Latency of TX:1T and RX:2T
- Power consumption : 0.158pj/bit
- Supports Parity generation and checking plus Lane repair
- Supports Read, Write and multi-Slave BIST
- Supports loopback and SCAN
- IP can be configured by APB, I2C, or JTAG interfaces
Technical Specifications
Foundry, Node
TSMC 5nm CLN5FF
Maturity
Pre-silicon
TSMC
Pre-Silicon:
5nm