IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL interconnect and Chip-on-Wafer-on-Substrate (CoWoS®) with silicon interposer. IGPD2DY01A contains 32 TX lanes and 32 RX lanes per slice and supports 8 slices in one PHY. Each TX/RX lane can support up to 16 Gbps data rate. In summary, IGPD2DY01A offers a full-duplex data transmission with extremely low power and up to 512 Gbps data rate per slice in both directions.
Each TX/RX slice contains PMA and PCS modules. PMA supports serialization, de-serialization, data transmission, eye training, and lane repair functions. PCS provides data bus inversion, CRC/Parity check, and FIFO functions. One PLL is also included in IGPD2DY01A to generate an 8 GHz high-speed clock for data transmission.
IGPD2DY01A is designed and fabricated in TSMC 5 nm FF CMOS process with 1.2 V analog supply voltage for PLL/PMA and 0.75 V analog/digital supply voltages. Independent low power mode for PLL and slices is available.
TSMC CLN5FF GLink 2.0 Die-to-Die PHY
Overview
Key Features
- 32 full-duplex lanes per slice
- 8 slices are included in the analog hard macro
- 1:8 mode with 256-bit data width or 1:16 mode with 512-bit data width for user interface
- VALID and READY handshake mechanism
- Flow control between TX and RX
- Data bus inversion
- CRC/Parity check
- Data replay to ensure no error found in RX
- Programmable data scrambling for smoothing current consumption profile
- Built-in test pattern and checker
- Lane repair
- EHOST: APB3, I2C, and JTAG register interface
- Built-in PLL
- 0.308 pJ/bit power consumption
- 1.2 V analog supply voltage for PLL/PMA and 0.75 V analog/digital supply voltage
- Independent low power mode for analog blocks
- Operating junction temperature: -40 °C ~ 125 °C
- Process: TSMC 5 nm 0.75 V/1.2 V CMOS LOGIC FinFET Process
- Metal Scheme: 1P15M (1X_h_1Xb_v_1Xe_h_1Ya_v_1Yb_h_5Y_vhvhv_2Yy_2R)
- 1P16M (1X_h_1Xb_v_1Xe_h_1Ya_v_1Yb_h_4Y_vhvh_2Yy_2Yx_2R)
- 1P17M (1X_h_1Xb_v_1Xe_h_1Ya_v_1Yb_h_5Y_vhvh_2Yy_2Yx_2R)
- Analog hard macro size: 3048.576 um x 744.968 um (2.271 mm2) for North-South direction macro and
- 746.283 um x 3047.268 um (2.274 mm2) for East-West direction macro
- Logic gate count: 2.8 M
- Supports both horizontal and vertical GDS orientation
Technical Specifications
Foundry, Node
TSMC 5nm CLN5FF
Maturity
Avaiable on request
TSMC
Pre-Silicon:
5nm