TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
Overview
IGPD2DZO1A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions, Integrated Fan-Out (InFO) with the RDL interconnect, and Chip-on-Wafer-on-Substrate (CoWoS@) with the silicon interposer.
Key Features
- 56 full-duplex lanes per slice
- 6-Slice/2-Slice PMA included in the analog hard macro
- Lane repair
- Data Bus Inversion (DBI)
- CRC/Parity Check
- Built-in test pattern and checker
- EHOST: APB3, I2C, and JTAG register interface
- Built-in PLL
Technical Specifications
Foundry, Node
TSMC CLN3FFE
Maturity
Avaiable on request
TSMC
Silicon Proven:
3nm
Related IPs
- TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC N5 X8, North/South (vertical) poly orientation
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC 12FFC X16, North/South (vertical) poly orientation
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC 12FFC X8, North/South (vertical) poly orientation
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC N5 X16, North/South (vertical) poly orientation
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC N6 X16, North/South (vertical) poly orientation