TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks
Overview
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations. It includes an optional digi logic circuitry which is required for high-speed operations. It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards.
Key Features
- Completely hardened PHY solution along with programmable delay chains & I/Os
- Fully selectable output impedance
- Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
- Automotive G1/G2 supported, ASIL-B certified
- Interoperability checks done with Synopsys Controllers
- HBM 2KV, CDM 500V(up to 7A), Latch-up +/-100 mA @ 125C
- Silicon validated IP
- Designed to support multiple metal stack options
- Support for flip-chip & wirebond packaging
Technical Specifications
Foundry, Node
TSMC 5nm - FF
Availability
Contact the Vendor
TSMC
Pre-Silicon:
5nm
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