TSMC 55nm USB2.0 Dual Role PHY
Overview
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB analog front-end with a build-in 8-bit/16-bit parallel interface, therefore, it is easy to interface with USB2.0 Device System. It can work either as a host PHY or as a device PHY, depending on the different setting from controller.
Key Features
- Process:TSMC 55nm Low Power Process
- Supply voltage: 1.08v~1.2v~1.32v, 2.25v~2.5v~2.75v, 2.97v~3.3v~3.63v
- Current consumption: < 50mA
- Operating junction temperature: - 40°C ~ +25°C ~ +125°C
Technical Specifications
Foundry, Node
TSMC 55nm
Maturity
Availiable on request
TSMC
Pre-Silicon:
55nm
FL
,
55nm
G
,
55nm
GP
,
55nm
LP
,
55nm
NF
,
55nm
ULP
,
55nm
ULPEF
,
55nm
UP