Trusted Platform Module (TPM) Verification IP

Overview

TPM Verification IP enables trust in computing the platforms in general. TPM Verification IP provides an smart way to verify the data transmission between TPM master and slave. The SmartDV's TPM Verification IP is fully compliant with Trusted Computing Group (TCG) Trusted Platform Module(TPM) Version 1.1b/1.2 and 2.0 Specification and provides the following features.

Trusted Platform Module (TPM) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Trusted Platform Module (TPM) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Full TPM master device and slave device functionality.
Compliant to the Trusted Computing Group (TCG) Trusted Platform Module(TPM) Version 1.1b/1.2 and 2.0 Specification
Compliant with TCG PC client-specific TPM Interface Specification (TIS) version 1.2/1.3
Hardware Asymmetric Crypto Engine.
Internal EEPROM Storage for RSA Keys.
Supports Low Pin Count (LPC), Serial Periferal Interface (SPI) and I2C interfaces.
- I2C Interface
- 400kHz Fast Mode/100kHz Standard Mode I2C Operation
- NV Storage Space for 2066 bytes of User Defined Data
- LPC Interface
- 33MHz LPC bus for easy PC interface
- NV storage space for 1756 bytes of user defined data
- SPI Interface
- SPI Protocol Up to 45MHz* (*Typical PC Operating Range is 24MHz to 33MHz)
- NV Storage Space for 2066 bytes of User Defined Data
Internal, high-quality Random Number Generator (RNG), HMAC, AES, SHA, and RSA Engines

Benefits

Faster testbench development and more complete verification of TPM designs.
Simplifies results analysis.
Easy to use command interface simplifies testbench control and configuration of transmitter and receiver.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the TPM testcases.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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