Time Sensitive Networking (TSN) Single Port End Node core

Overview

The TSN End Node IP core from NetTimeLogic is a standalone Time Sensitive Networking (TSN) single port end node core according to IEEE 802.1 and IEEE 1588 standards. It supports the same features as the TSN Network Node (switched endpoint) core except network redundancy. It is meant as a TSN co-processor enabling non-TSN aware interfaces (e.g. legacy or "normal"MAC) to support TSN features like scheduling, priority queues, credit shaping, cyclic forwarding and preemption. The core is intercepting the path between the Ethernet PHY and an Ethernet core that forwards or handles Ethernet frames (MAC, PHY or Switch). In addition, it has up to 8 streaming ports which allow to send and receive frames directly from the specific priority queues and phases.

All tables, protocols and algorithms are implemented completely in HW in the core, no CPU is required, except for configuration. This allows running TSN protocols completely independent and standalone from the user application.

Key Features

Up to 8 different priority queues, with freely definable VLAN priorities
Up to 8 phases per cycle according to priority queues
Cycle time and phase durations freely configurable (max 1 ms)
Frame scheduling according to IEEE 802.1 Qbv
Cyclic forwarding according to IEEE 802.1 Qch
Credit based shaper according to IEEE 802.1 Qav
Frame preemption according to IEEE 802.1 Qbu and IEEE 802.3 br can be enabled for the lowest priority to allow maximum bandwidth usage
Registerset to configure according to IEEE 802.1 Qcc
Synchronization with sub-microsecond accuracy according to IEEE 1588 Default-, Utility- or Power-Profile or according to IEEE 802.1 AS
One external port, one internal/interlink port. Interlink port is optional when AXI stream interfaces are used
Intercepts path between MAC and PHY
Supports up to 8 AXI streaming interfaces, one for each priority/phase
Full line speed
AXI4 Light register set or static configuration
MII/RMII/GMII/RGMII Interface support
Optional frame and error counters

Benefits

Coprocessor handling TSN completely standalone in the core.
No Software Stack required

Block Diagram

Applications

Distributed data acquisition
Ethernet based automation networks
Automation
Robotic
Automotive
Test and measurement

Deliverables

Source Code (not encrypted, not obfuscated)
Reference Designs
Testbench with Stimulifiles
Configuration Tool
Documentation

Technical Specifications

Availability

Now

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