This is fully configurable FIFO with configurable Depth, Configurable width. Fifo Memory is implemented by Registers.
It has option to select CDC mythology and CDC Clock ratio to make it more stable operating at different set of freq.
This is a Generic fifo with configurable Depth, Configurable Width and Different Clock Domain Crossing options.
Overview
Key Features
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
Benefits
- 1. Fully stable operation.
- 2. Non-2**n depth supported.
- 3. Dip-In and Data Available support.
- 4. CDC method and CDC clock ratio selectable
Applications
- Internal IP Component Block
- can be used inside any IP/SOC.
Deliverables
- Standard Deliverables list -
- 1. Source Code in verilog.
- 2. Test Bench.
- 3. Simulation Scripts.
- 4. Synthesys scripts.
- 5. Documentation
- 6. User Guide.
Technical Specifications
Maturity
Final, Stable, Tested
Availability
Avaliable
Related IPs
- This is collection of Synchronization Components can be used to synchronize across different clock domains for control and Data Transfer
- This is a Collection of different kind of FIFOs and Elastic buffers.
- 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- This is GPIO Block Configurable on AMBA APB/ AHB Interface with wide configuration option
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- Configurable UART with FIFO