This is a Collection of different kind of FIFOs and Elastic buffers.

Overview

This is a collection FIFO and Elastic Buffers.

This carry following kind of FIFO and Elastic Buffers -

1. First In First Out (FIFO) (Sync/Async) with internal Registers.
2. First In First Out (FIFO) (Sync/Async) with OnChip Dual Port SRAM.
3. First In First Out (FIFO) (Sync) with OnChip single Port SRAM.
4. Elastic Buffer

Key Features

Features -
This is a Generic fifo with configurable Depth, Configurable Width and Clock Domain Crossing options.
Fully Stable, CDC Proven, Non2**n depth supported FIFOs.

Benefits

1. Using Stable and Tested Standard block decrease time to clean up issues in later stages.
3. Makes IP More stable to operate.

Applications

Internal IP Component Block
can be used inside any IP/SOC.

Deliverables

Standard Deliverables list -
1. Source Code in verilog.
2. Test Bench.
3. Simulation Scripts.
4. Synthesys scripts.
5. Documentation
6. User Guide.

Technical Specifications

Maturity

High, Stable, Tested

Availability

Avaliable

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