This is fully configurable FIFO with configurable Depth, Configurable width. Fifo Storage Memory is implemented by External Dual Port Memory.
It has option to select CDC mythology and CDC Clock ratio to make it more stable operating at different set of freq.
This fifo access external OnChip dual port memory to store data.
Overview
Key Features
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. External Dual Port Memory for Storage
Benefits
- 1. Fully stable operation.
- 2. Non-2**n depth supported.
- 3. Dip-In and Data Available support.
- 4. CDC method and CDC clock ratio selectable.
- 5. Good memory packing density help user to implement large FIFOs
Applications
- Internal IP Component Block
- can be used inside any IP/SOC.
Deliverables
- Standard Deliverables list -
- 1. Source Code in verilog.
- 2. Test Bench.
- 3. Simulation Scripts.
- 4. Synthesys scripts.
- 5. Documentation
- 6. User Guide.
Technical Specifications
Maturity
Final, Stable, Tested
Availability
Available
Related IPs
- This fifo uses external onchip single port memory to store data.
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- IEEE1149.1-2001 JTAG access port
- Direct Memory Access Controller IP Core
- I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface
- QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)