TCP/UDP/IP Network Protocol Accelerator Platform

Overview

Accelerate Network Protocols with FPGA TCP/UDP/IP Stack

The German Fraunhofer Heinrich-Hertz-Institute (HHI) has partnered with MLE to market the proven network accelerators “TCP/IP & UDP Network Protocol Accelerator Platform (NPAP)”.  This customizable solution enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for 1G / 2.5G / 5G / 10G / 25G / 40G / 50G / 100G Ethernet links.

MLE is a licensee of Fraunhofer HHI, and offers a range of technology services, sublicenses and business models compatible with customer’s ASIC or FPGA project settings, world-wide.

Key Features

  • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
  • Full line rate of 70 Gbps or more in FPGA, 100 Gbps or more in ASIC
  • 128-bit wide bi-directional data paths with streaming interfaces
  • Multiple, parallel TCP engines for scalable processing
  • Network Interface Card functionality with Bypass (optional)
  • DPDK Stream interface (optional)
  • Corundum NIC integration with performance DMA and PCIe (optional)

Benefits

  • Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”)
  • Increase network throughput and reduce transport latency
  • Bring full TCP/UDP/IP connectivity to FPGAs even if no CPU available (“Full Acceleration”)
  • Complete and customizable turn-key solutions and IP cores based on the TCP/UDP/IP stack from the Fraunhofer HHI
  • All MAC / Ethernet / IPv4 / UDP / TCP processing is implemented in HDL code, synthesizable to modern FPGAs and ASIC
  • User applications can either be implemented in FPGA logic or in software via application-specific interfaces to CPUs

Block Diagram

TCP/UDP/IP Network Protocol  Accelerator Platform Block Diagram

Applications

  • FPGA-based SmartNICs
  • In-Network Compute Acceleration (INCA)
  • Hardware-only implementation of TCP/IP in FPGA
  • PCIe Long Range Extension
  • Networked storage, such as iSCSI
  • Test & Measurement connectivity
  • Automotive backbone connectivity based on open standards
  • Video-over-IP for 3G / 6G / 12G transports
  • Increase throughput for 10G/25G/50G/100G Ethernet
  • Reduce latency in System-of-Systems communication

Technical Specifications

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Semiconductor IP