For embedded developers seeking to hinder physical tampering and achieve a higher level of security certification, Arm offers the Cortex-M35P: a robust, high-performing processor. It builds upon the proven Arm Cortex-M technology deployed in billions of SoCs, making physical and software security accessible for all developers.
Physical security is generally complex – however, the ease-of-use of the Cortex-M35P processor, combined with the support of Arm and the Arm ecosystem, now open the door for embedded developers to deliver many new devices with physical resilience at the heart.
Tamper-resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M
Overview
Key Features
- Architecture: Armv8-M Mainline (Harvard)
- ISA Support: Thumb/Thumb-2
- Pipeline: Three-stage
- Software security: Optional TrustZone for Armv8-M, stack pointers checking
- Physical security: Built-in protection from invasive and non-invasive attacks
- DSP Extensions
- Optional DSP/SIMD instructions
- Single cycle 16/32-bit MAC
- Single cycle dual 16-bit MAC
- 8/16-bit SIMD arithmetic
- Floating Point Unit
- Optional single precision floating point unit
- IEEE 754 compliant
- Co-processor interface: Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
- Memory Protection: Optional Memory Protection Unit (MPU) with up to 16 regions per security state
- Interrupts: Non-Maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
- Wake-up Interrupt Controller: Optional for waking up the processor from state retention power gating or when all clocks are stopped
- Sleep Modes: Integrated Wait for Event (WFE) and Wait for Interrupt (WFI) instructions with Sleep On Exit functionality
- Debug: Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
- Trace: Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)
- Cache: Instruction cache
Benefits
- Cortex-M35P extends the anti-tampering features of the SecurCore family of processors, making this state-of-the art technology available to Cortex-M developers. Robust embedded security is more accessible than ever with the benefits of both physical and software security, using the optional TrustZone isolation.
Block Diagram

Applications
- Payment
- Integrated or Embedded Secure Elements
- Secure embedded applications
- IoT
- Industrial
- Automotive
- Healthcare
- Medical
- Biometric data
Technical Specifications
Related IPs
- Highest code density, Low Power 32-bit Processor with optional DSP
- I2C Controller IP – Slave, SCL Clock only, principally for configuring registers in mixed-signal ICs with low noise or low power requirements
- Very Low gate Count, Hardware level, Software Data Isolation and Master level Data protection engine.
- Digital Signal Processor Software compatible with the TI 320C50, 320C51, 320C52 and 320C53
- Fast Quantum Safe Engine for ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) with DPA
- Self-contained cryptographic subsystem designed for PQC + classical, minimal integration effort, with SCA protection