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SWD Verification IP

Overview

SWD(Serial Wire Debug) Verification IP provides an efficient and simple way to debug and trace functionality on processor cores and System on Chip (SoC) devices. The SmartDV's SWD Verification IP is fully compliant with ARM Serial Wire Debug interface Specification and provides the following features.

SWD Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SWD Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports ARM Serial Wire Debug Interface specifications.
  • Full SWD Host and Device functionality.
  • Supports single bidirectional data connection and a separate clock to transfer data synchronously.
  • Supports START and STOP bit generation and handling.
  • Supports DP or AP register accessing.
  • Supports WAIT response to read or write operation request.
  • Supports FAULT response to read or write operation request.
  • Supports Line reset.
  • Supports Header and Data parity generation.
  • Supports Header and Data parity error checks.
  • Supports Sticky overrun behavior.
  • Supports SW-DP write buffering.
  • Supports insertion of errors on below
    • Stop bit
    • Park bit
    • Random Write NACK insertion by Device
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Callbacks in Host and Device for various events.
  • Functional coverage of complete SWD specs.
  • SWD Verification IP comes with complete testsuite to test every feature of SWD specification.

Benefits

  • Faster testbench development and more complete verification of SWD designs.
  • Easy to use command interface simplifies testbench control and configuration of Host and Device.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

SWD Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the SWD testcases to certify SWD Host/Device device.
  • Examples showing how to connect various components, and usage of Host, Device and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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