SVID Verification IP

Overview

SVID Verification IP provides an smart way to verify the SVID bi-directional two-wire bus. The SmartDV's SVID Verification IP is fully compliant with the version 1.2 SVID Specifications and provides the following features.

SVID Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SVID Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Implemented in Unencrypted OpenVera and SystemVerilog.
Supported RVM, AVM, VMM and non-standard verify env.
Supports SVID specification version 1.2 and SVI3 specification version 1.01.
Full SVID Master and Slave functionality.
Supports send byte command as per the SVID specification.
Supports following operation as per the SVI3 specification

Slave enumeration and addressing
Command packet framing
Global commands
Back to back packet framing
Telemetry stream processing

Supports programmable clock frequency of operation.
Support Timeout detection and generation.
Supports clock synchronization.
Supports communication Error Catching and Recovery
Glitch insertion and detection.
Callbacks in master, slave and monitor for user processing of data
Supports insertion of errors

Master abort in middle of transaction.
Illegal command transaction.
Random and Periodic clock period stretching by slave.
Timeout error insertion.
Glitch insertion.

Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
SVID Verification IP comes with complete testsuite to test every feature of SVID specification.

Benefits

Faster testbench development and more complete verification of SVID designs.
Easy to use command interface simplifies testbench control and configuration of Master and Slave.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the SVID testcases to certify SVID Master/Slave device.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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