SVID Verification IP provides an smart way to verify the SVID bi-directional two-wire bus. The SmartDV's SVID Verification IP is fully compliant with the version 1.2 SVID Specifications and provides the following features.
SVID Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SVID Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.