IP Catalog > Interface IP > Interconnect IP > PCI IP > PCI Express IP > PCI Express Controller IP > Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications

Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications

Overview

The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be configured for dual-mode applications supporting runtime-selectability between device and host mode. The configurable and scalable IP supports all key required features of the CXL 3.0 specification and full backward compatibility with CXL 2.0, 1.0 and 1.1 specifications. The IP also supports PCI Express (PCIe) 6.0, 5.0, 4.0, and 3.1 specifications, and can be easily connected to a Synopsys 64GT/s PHY through the built-in PIPE 6.x interface. The CXL controller supports Synopsys’ MultiStream architecture, offering multiple application interfaces for maximum throughput efficiency across various link widths and payloads. The high-quality, synthesizable IP is optimized for maximum throughput and minimum latency in a 64GT/s x16 configuration, but can be configured to support CXL port bifurcation and degraded modes, as well as all 3 defined CXL device types for maximum application flexibility. The Synopsys CXL Controller IP integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interfaces or industry standard AMBA interfaces, with conservative timing suitable for a wide range of ASIC and FPGA technologies.

Key Features

  • Supports key required features of the CXL 3.0 specification and full backwards compatibility with CXL 2.0, 1.0 and 1.1
  • Supports PCIe 6.0 mode with 64 GT/s and x16 link width
  • CXL license includes PCIe 6.0 functionality and fallback mode
  • Customers using CXL do not need an additional PCIe 6.0 license
  • Fully supports PCIe 6.0 base specification
  • Supports PIPE 6.X Interface for connection to 64 GT/s PCIe 6.0 PHYs
  • PCIe/CXL.io application interface with the Synopsys native interface or the optional Arm AMBA 4 AXI and AMBA 3 AXI
  • Choice of interfaces optimized for CXL.cache and CXL.mem - either the Synopsys Native CXL interface or the Arm AMBA CXS interface
  • Supports operation at x16, x8, x4, x2, and x1
  • CXL host and device support, with dual mode capability to enable selection of Device and Host mode at runtime
  • CXL switch port support for enabling embedded switches
  • Implements CXL.io, CXL.mem, and CXL.cache protocols
  • Supports all 3 defined CXL device types for maximum design flexibility
  • High-speed CXL.cache/mem interfaces for minimum latency
  • Highly efficient flit-packing algorithm
  • Optional Drift buffer for reduced latency
  • Multiple CXL.cache device to host request and Response interfaces to maximize throughput
  • Multiple CXL.mem Subordinate to Master Response/No Response channels for enhanced throughput
  • Supports Data Poisoning by transmitter
  • Address Translation Services (ATS)
  • PCIe Advanced Error Reporting (AER)
  • Supports deferrable writes
  • Removal of sync header from Ordered set blocks in latency optimized mode.
  • Supports PCIe Alternate Protocol
  • PCIe Port, Device, and Compliance Designated Vendor-Specific Extended Capabilities (DVSEC) for CXL.
  • CXL upstream port RCRB with registers from PCIe upstream ports, configuration header and PCIe capabilities
  • CXL upstream port MEMBAR0
  • FLR support for CXL.io
  • Supports CXL containment feature (“Viral”)
  • Special performance enhancement features for advanced Arm-based servers, including LTI, MSI-GIC interfaces
  • Industry-leading Reliability, Availability and Serviceability (RAS) features extended to support new CXL features
  • Selected PCIe 6.0 supported features:
  • Supports all required features of the PCIe 6.0, 5.0, 4.0 and 3.1 specifications
  • Full transaction layer, data link layer and physical layer
  • Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes (CXL supports only 8.0, 16.0, 32.0 and 64 GT/s data rates)
  • Available in 1024-bit, 512-bit and 128-bit datapath widths
  • Optional embedded DMA controller with up to 64 read and 64 write channels for high-throughput with minimal SoC resource overhead
  • Supports optional ECNs

Benefits

  • Supports all key required features of the CXL 3.0 spcification and full backwards compatibility with CXL 2.0, 1.0 and 1.1
  • Supports all required features of the PCI Express 6.0 (64GT/s), 5.0 (32 GT/s), 4.0
  • (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit)
  • specifications
  • Application interface includes the Synopsys native interface with optional Arm® AMBA® 5 AXI, AMBA 4 AXI and
  • AMBA 3 AXI interface support for CXL.io
  • CXS interface support option
  • Expanded 1024-bit architecture based on silicon-proven 512-bit PCIe 6.0 controller design
  • Available with performance enhancement features for advanced Arm-based servers
  • Available with Integrity and Data Encryption (IDE) security support with optional IDE Security Modules
  • Standards-compliant Synopsys IDE Security Modules protect data transfer and are pre-verified with Synopsys Controllers for CXL 3.0/2.0 and PCI Express 5.0/6.0 for fast integration and low risk
  • TDISP support for CXL.io for Single-Root I/O Virtualization (SR-IOV) and hardware security via IDE

Applications

  • AI/machine learning
  • High-performance networking
  • Media/graphics
  • Memory expansion
  • General purpose acceleration

Deliverables

  • The coreConsultant utility to guide designers through the installation configuration, verification, and implementation of the IP; Verilog RTL code; Example PHY interfaces; ASIC and FPGA synthesis scripts; Verification environment; Synopsys Verification IP for PCIe; Documentation: release notes, installation/integration guide, application notes, user manual

Technical Specifications

Maturity
Available on request
Availability
Available
Request Info

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