AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMA-FD)”, “C” 16-bit compression, “B” bit manipulation, “K” (scalar crypto), CMO extensions, and Andes performance enhancements. It features MMU for Linux based applications, TAGE branch prediction for accurate branch execution, 4 wide instruction decode, 8 independent functional pipelines (4 integer, 2 fp, 2 load/store), level-1 instruction/data caches for low-latency accesses. The AX65 symmetric multiprocessor supports up to eight cores and a level-2 cache controller with instruction and data prefetch. Coherence Manger ensures data coherence among CPU accesses and IO transactions from cacheless bus masters. Other features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, StackSafe™, and PowerBrake and WFI for power management.
Superscalar Out-of-Order Execution Multicore Cluster
Overview
Key Features
- 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
- Symmetric multiprocessing up to 8 cores
- Level-2 cache and coherence support
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant to RISC-V GCB, scalar cryptography and CMO extensions
- RVA22 profile compliant
- 64-bit architecture for memory space over 4GB
- TAGE Branch predication for highly accurate prediction
- Linux-capable Memory Management Unit (MMU)
- Physical Memory Protection (PMP) and latest architecture enhancement extension (Smepmp) for access permission controls
- Andes-enhanced Platform-Level Interrupt Controller (PLIC) for a wide range of system events and real-time performance
- ECC or Parity for SRAM error protection
- StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
- PowerBrake and WFI (Wait for Interrupt) for different power saving occasions
Benefits
- Performance
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Andes extensions, architected for performance and functionality enhancements
- 64-bit, 13-stage pipeline CPU architecture
- 16/32-bit mixable instruction format for compacting code density
- 4 wide frontend decode to optimize instruction throughput
- 128-entry out-of-order execution to fully utilize the computation resources
- 8 pipelines to explore instruction parallelism
- Branch prediction to optimize performance on conditional jumps
- Return Address Stack (RAS) to speed up procedure returns
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for real-time performance and a wide range of system usages
- Security
- Physical Memory Protection (PMP) and latest architecture enhancement extension (Smepmp) for access permission controls
- Flexibility
- Easy arrangement of preemptive interrupts
- StackSafe™ hardware to detect runtime overflow/underflow
- ECC on cache memories for fault protection
- Power Management
- PowerBrake and WFI (Wait For Interrupt) for power management at different occasions
Block Diagram
Applications
- High performance computing
- Networking
- Data Storage
- TV or Setop box
Technical Specifications
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