Streaming pipelined FFT

Overview

A highly efficient pipelined radix-2 squared FFT. Ported to both ASIC and FPGA technology and achieving a very high clock speed with minimal logic and memory.

Also available is a variant with single bit width growth per stage which does not require per-sample exponents.

EnSilica has a comprehensive range of FFT IP cores, these cores can be configured to replace the AMD FFT LogiCORE™ IP or FFT Intel® FPGA IP Core when migrating an FPGA design to ASIC technology.

Key Features

1 clock cycle per point, no gap required between packets
Run-time selection of any power of 2 FFT points
Run-time selection of forward or inverse transform
Internal convergent rounding
AXI4 streaming interface
Per sample exponent for maximum dynamic range
Parameterized maximum transform length
Parameterized bit widths
Parameterized for bit-reversed or natural order output
Single ported RAMs for ASIC or dual ported for FPGA

Benefits

Run time selection of transform size
Common code for FPGA and ASIC simplifies prototyping
Can be parameterized for exact requirements
Delivered with memories ported to your technology node

Applications

Radar
Wireless Comms
Wired Comms
MIMO
OFDM systems

Deliverables

RTL
Testbench
Synthesis scripts
Documentation
MATLAB and C++ bit exact model
CUDA accelerated bit exact model

Technical Specifications

Availability

Available Now

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