Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 28nm HLP process
Overview
UMC 28nm Logic and Mixed-Mode HLP/HVT process 12-Track POWERSLASH Cell Library (C35).
Technical Specifications
Foundry, Node
UMC 28nm HLP
UMC
Pre-Silicon:
28nm
HLP
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