SRIOV Verification IP

Overview

Key Features

• Supports SRIOV specs 1.0/1.1.
• Supports PCIE Express specs 1.0/2.0/3.0/4.0/5.0.
• Supports PIPE, Serial, PCS/PMA, Low pin count and SerDes interface.
• Supports UVM and Verilog APIs supplied , as well as C DPI exports
• Supports for Gen 1,2,3,4 and 5 including SSC
• Supports Full link speed and width negotiation up to 32 Lanes.
• Supports Automated Error Injections at all layers.
• Supports Checkers verify protocol timing checks and functional accuracy at each layer.
• Supports Queuing for 8 VCs with configurable depth.
• Supports Configurable TC to VC queue mapping.
• Supports for multiple Requestor / Completer applications, including user supplied applications.
• Supports User interface for direct TLP queuing and receipt.
• Supports Checks all TLPs for correct formation of headers, prefixes and ECRC.
• Supports Full DL state machines.
• Supports Checks all framing, LCRC, and lane rules.
• Supports Check all DLLP fields and formatting.
• Supports Interface to send / receive user defined DLLPs.
• Supports ASPM and Software controlled Power Management.
• Supports Automated Error Injections and checking.
• Supports Full LTSSM state machine.
• Supports SERDES model with digital clock recovery.
• Supports Speed and Link Width negotiation.
• Supports Upconfigure, polarity inversion, and lane-to-lane skew.
• Supports Configurable Spread Spectrum Clocking (SSC).
• Supports Gen 1 & 2 PCS, 8b/10b encoding.
• Supports Gen 3, 4 & 5 128/130 encoding.
• Supports Configurable timers and timeouts.
• Callbacks in Root complex,End point and monitor for user processing of data.
• Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
• SRIOV Verification IP comes with complete testsuite to test every feature of SRIOV and PCI Express specification.
• Supports scoreboard checking
• Built-in monitors for protocol checking, including a global bus monitor.
• Functional coverage to cover all functionality of SRIOV and PCIE Root complex and End point.
• Supports for multiple instantiations to create complex verification environment.
• Supports IOV Re-Initialization and Reallocation
• Supports VF Migration

Benefits

• Faster testbench development and more complete verification of SRIOV and PCI Express designs.
• Easy to use command interface simplifies testbench control and configuration of Root complex and End point.
• Simplifies results analysis.
• Runs in every major simulation environment.

Block Diagram

Deliverables

• Complete regression suite containing all the SRIOV testcases to certify SRIOV and PCI Express Root complex and End point.
• Examples showing how to connect various components, and usage of BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

Technical Specifications