SPI4.2
Overview
The SPI4 Intellectual Property (IP) core enables user instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) cores in Lattice Field Programmable Gate Arrays (FPGAs). The SPI4 IP core supports up to 256 data channels with aggregate throughputs of between 3 and 12.8Gbps and can be used to connect network processors with OC192 framers, mappers, and fabrics, as well as Gigabit and 10-Gigabit Ethernet MACs.
Key Features
- The Soft SPI4 IP core is fully compliant with the OIF System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) interface standard
- Supported through Diamond or ispLEVER IPexpress™ tool for easy user configuration and parameterization
- Supports up to 256 independent channels
- 400 to 500MHz DDR Dynamic mode operation in LatticeSC and LatticeSCM devices
- 156 to 350MHz DDR Static timing mode operations for LatticeECP3 devices. Supports non-standard “SPI4 Lite” line rates.
- Supports both 64b and 128b internal architectures for optimization of either speed or size
- Requires only ~2000 slices (64b mode) for a full 256-channel Static mode core
- Supports full bandwidth utilization of the SPI4 line in both directions - requires no idle cycles in the receive direction or insertion of idles in the transmit direction between bursts (as long as there is data available)
- Parity error checking/generation on all receive and transmit control and data words (DIP4) and status (DIP2) interfaces
- Parity error force capabilities on data (independent controls: control word and data) and status interfaces
- Various run-time user controls
- Force idles (transmitter)
- Enable/disable packing (transmitter)
- Training pattern (CAL_M, MAX_T)
- Complete run-time programmability of all internal FIFO thresholds for efficient management of SPI4 line in terms of Lmax and packing
- Provides a direct interface to primary device I/O at the SPI4 interface and an internal FIFO interface to user logic
- Supports minimum transmit burst sizes in increments of 16 bytes from 16 bytes up to 1008 bytes for optimized network processor applications
- Support for packet sizes down to 4 bytes in length
- Fully configurable 512-location calendar RAM for Rx and Tx directions and associated 256-location status RAMs
- Two independently configurable methods of status reporting in the receive and transmit directions - RAM addressable and Transparent
- Rising or falling edge selectable Status Channel I/O independently configurable in the receive and transmit directions
Block Diagram
