IP Catalog > Peripheral IP > SPI IP > SPI (Serial Peripheral Interface) Assertion IP

SPI (Serial Peripheral Interface) Assertion IP

Overview

SPI (Serial Peripheral Interface) Assertion IP provides an efficient and smart way to verify the SPI designs quickly without a testbench. The SmartDV's SPI Assertion IP is fully compliant with standard SPI Specification and provides the following features.

SPI (Serial Peripheral Interface) Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPI (Serial Peripheral Interface) Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Follows SPI specification as defined in SPI Block Guide 4.01.
    • Supports SQI interface specification and common flash device models
    • Supports data width from 4 bits to 64 bits.
    • Support Master and Slave Mode
    • Supports 3-wire ,4-wire SPI interface
    • Supports bus width 1 bit and 4 bit
    • Slave device supported for SPI 3 wire are
    • BOSCH SMB380
    • RICOH R2033K
    • Support baud rate selection
    • Support internal clock division check.
    • Support clock polarity (CPOL) selections.
    • Support clock phase (CPHA) selection.
    • Support single and burst transfer mode.
    • Detects and reports the following errors.
    • Mode Fault error
    • In standard model mode, Mater/Slave support different types of devices. Like FLASH, EEPROM,FRAM,RTC,SQI,MOTOROLA MODE, NS MODE, TI MODE(PRECEDE and COINCIDE), EMPSPI, MACRONIX, DBI TYPE C and serial flash
    • Supports single,dual and quad mode bus width operation
    • Supports spansion DDR model
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV SPI VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure SPI Assertion IP functionality.

    Benefits

    • Runs in every major formal and simulation environment.

    Block Diagram

    SPI (Serial Peripheral Interface) Assertion IP Block Diagram

    Deliverables

    • Detailed documentation of Assertion IP usage.
    • Documentation also contains User's Guide and Release notes.

    Technical Specifications

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