Octal SPI (Serial Peripheral Interface) Verification IP

Overview

Octal SPI is the serial synchronous communication protocol developed by Macronix(CMOS MXSMIO®(SERIAL MULTI I/O) Flash memory).It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

Octal SPI (Serial Peripheral Interface) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Octal SPI (Serial Peripheral Interface) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Follows Octal SPI basic specification as defined in Macronix (CMOS MXSMIO®(SERIAL MULTI I/O) Flash memory).
Supports Master and Slave Mode.
Supports Serial Peripheral Interface -- Mode 0
Supports below Protocol modes
- Single I/O and Octa I/O
- Support DTR (Double Transfer Rate) Mode
Supports clock frequency up to
- Single I/O mode: 133MHz
- Octa I/O mode: 133MHz
Supports below Input Data Format
- SPI: 1-byte command code
- OPI: 2-byte command code
Supports below Advanced Security Features
- Block lock protection
- Advanced Sector Protection (Solid and Password Protect)
Supports below Additional 8K bit security OTP
- Features unique identifier
- Factory locked identifiable, and customer lockable
Supports Command Reset.
Supports Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID.
Supports Serial Flash Discoverable Parameters (SFDP) mode.
Supports 11-wire Slave interface.
Supports data width upto 8 bits.
Supports baud rate selection.
Supports single and burst transfer mode.
Supports constraints Randomization.
Supports backdoor initialization of data.
Built in functional coverage analysis.
Status counters for various events on bus.
Supports Callbacks in Master, Slave and Monitor for various events.
Octal SPI Slave can be configured as standard device or can use FIFO for data passing.
Master contains rich set of commands for both standard device and FIFO model mode.

Benefits

Faster testbench development and more complete verification of Octal SPI designs.
Easy to use command interface simplifies testbench control and configuration of Slave and Master.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the Octal SPI testcases.
Examples showing how to connect various components and usage of Master, Slave and Monitor.
Detailed documentation of all classes, tasks and functions used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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