SPI/SERIAL FLASH Verification IP

Overview

SPI/SERIAL FLASH Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV's SPI/SERIAL FLASH Verification IP is fully compliant with SPI Block Guide V04.01 of the Motorola's M68HC11 user manual rev 5.0 SPI-Bus Specification and serial flash sst25vf064c,sst25vf512 and sst25wf080 Specification and provides the following features. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

SPI/SERIAL FLASH Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPI/SERIAL FLASH Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Follows Serial Flash basic specification as defined in serial flash sst25vf064c,sst25vf512 and sst25wf080
Support Master and Slave Mode
Supports data width of 8 bit
Support baud rate selection
Supports standard, fast, and high speed operations.
Supports flexible erase operation like,
- 4KByte sector erase.
- 8KByte block erase.
- 32KByte block erase.
- 64KByte block erase.
Support internal clock division check.
Support clock polarity selections and Clock Phase selection.
Support single and burst transfer mode.
Support on the fly generation of data.
Supports constraints Randomization.
Supports Auto Address Increment (AAI) Programming
Supports Write protection mode
Glitch insertion and detection
Built in functional coverage analysis.
Supports backdoor initialization of data.
Status counters for various events on bus.
Supports single,dual bus width operation
Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on Serial Flash.
Serial Flash Slave can be configured as standard device or can use FIFO for data passing.
Master contains rich set of commands for both standard device and FIFO model mode.

Benefits

Faster testbench development and more complete verification of Serial Flash designs.
Easy to use command interface simplifies testbench control and configuration of slave and master.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the SPI/SERIAL FLASH testcases.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

Request Info