Xilinx provides a SPDIF Controller to transport audio data.
The Sony/Philips Digital Interconnect Format (SPDIF) core is a digital audio interface controller that implements the International Electronic Commission (IEC) 60958-3 interface for transmitting and receiving audio data. This includes standard bus interfaces to the AMBA® AXI4-Lite and AXI4-Stream interfaces, allowing for integration to the IP core with a master system for further processing of audio data. Data collected by the LogiCORE™ IP SPDIF core is stored in the core’s internal FIFO, allowing the system to process a relatively slow audio stream.
SPDIF
Overview
Key Features
- Configurable as an SPDIF audio data transmitter or an SPDIF audio data receiver
- Configurable FIFO buffer stores the audio sample data CRC checking or insertion for transmitted frames
- IEC 60958-3 standard SPDIF digital audio bus interface
- Audio sample lengths of 16/20/24 bits
- Variable sampling rates (32 kHz/44.1 kHz/48 kHz/88.2 kHz/96 kHz/176.4 kHz/192 kHz)
- Based on AXI4-Stream specification
- Continuous aligned streams only (no null or positional bytes transmission support)
- Register access support through the AXI4-Lite interface
Technical Specifications
Related IPs
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
- SPDIF IP
- SPDIF-Rx-Pro : Configurable SPDIF-AES/EBU Receiver
- SPDIF-Tx-Pro : Configurable SPDIF/AES3 Transmitter