Spatial image transformation accelerator

Overview

The Spatial image transformation core is a signal processing accelerator designed for single or multi-channel image manipulations based on matrix multiplication. The core is packaged as an AXI-Stream compatible accelerator, which features a bi-cubic interpolation for reconstruction and parallel access to embedded dual port memory resources for row buffering. RGB or single channel pixel patterns with 8/10/12 bit depths are available for configuration and resolution is adjustable post implementation. Resource critical parameters, such as memory size, are variable to optimize the architecture for different types of transformations.
The Spatial image transformation core is packaged for the Xilinx IP Integrator tool and can be combined with other Xilinx IP cores. The parameters are completely configurable in the module allowing the designer to adjust for different image processing pipelines.

Key Features

  • Streaming is compatible with AXI-Stream protocol
  • Transformation and image dimension parameters are configurable through AXI4-Lite
  • Configurable image resolution and transformation coefficients supporting resolutions - up to 8192x8192.
  • Single channel or RGB pixel patterns
  • Supports 8/10/12 bit depths
  • Available for Xilinx Vivado® IP Integrator

Benefits

  • Can be integrated with other AXI-Stream compliant image processing cores
  • Input and output dimensions are configurable independently for convenient resizing operations
  • Efficient buffering with parallel memory access scheme

Block Diagram

Spatial image transformation accelerator Block Diagram

Applications

  • Image geometric transformations, resizing and cropping

Deliverables

  • Encrypted IP Integrator core
  • Testbench
  • Test case
  • Documentation

Technical Specifications

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Semiconductor IP