SpaceWire Verification IP

Overview

The SpaceWire Verification IP is compliant with ECSS-E-ST-50-12C specification and verifies SpaceWire interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.

SpaceWire Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SpaceWire Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant with ECSS E‐ST‐50‐12C Standard.
Supports speeds between 2 Mb/s and 400 Mb/s.
Supports sending packets of information from a source node to a specified destination node.
Supports full-duplex point-to-point serial data communication links.
Supports Data-Strobe (DS) encoding.
Supports encoding/decoding Link interface.
Supports flow control and link Initialization.
Includes Time-Codes support.
Supports all types of errors insertion/detection as given below:

Link Errors
Disconnect error
Parity error
Escape sequence error
Character sequence error
Credit error
Empty packet error
Network Errors
Link error
EEP received error
Destination address error

Provides link error recovery.
Supports exchange of silence error recovery procedure.

Arbitration schemes supported:
Priority based
Round‐robin
Random arbitration
First come first served

On-the-fly protocol and data checking.
Compliant with Spacewire RMAP standard ECSS E‐ST‐50‐52C.
Complete RMAP protocol handling core with memory interface.
Configurable burst transfer depth, RMAP data byte order, internal FIFO sizes,verify buffers size.
RMAP supports following commands

Write
Read
Read-Modify-write

Notifies the test bench of significant events such as transactions, warnings and protocol violations.
Status counters for various events on bus.
Callbacks in Host and Node for various events.
Built in functional coverage analysis.
SpaceWire Verification IP comes with complete testsuite to verify each and every feature of SpaceWire specification.

Benefits

Faster testbench development and more complete verification of SpaceWire designs.
Easy to use command interface simplifies test bench control and configuration of Host and Node.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the SpaceWire testcases.
Examples showing how to connect various components, and usage of Host, Node and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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