SpaceWire CODEC

Overview

The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C).

Data is transmitted and received through 9-bit wide FIFOs with configurable depth. The core also provides an interface for transmitting and receiving Time-codes as well as configuring the link properties such as the link rate.

For critical space applications, a fault-tolerant (FT) version of GRSPW_CODEC is available with full SEU protection of all RAM blocks.

Key Features

  • Full implementation of SpaceWire standard (ECCS-E-ST-50-12C)
  • Simple 9-bit wide FIFO host interface
  • Redundant port
  • SEU protection fault-tolerance

Benefits

  • Tested and verified against several other SpaceWire cores
  • High frequency
  • Easily portable between FPGA and ASIC
  • Low-cost project license
  • SEU protection of all RAM blocks

Block Diagram

SpaceWire CODEC Block Diagram

Deliverables

  • Encrypted RTL
  • Stand-alone testbench
  • User's manual

Technical Specifications

×
Semiconductor IP