For many current and emerging high data rate applications such as 4G, 5G and DOCSIS3.1 Cable Access, transmission reliability is a key success factor to support the quality of the overall system. A high performance Soft-Decision FEC (i.e. >1Gbps), is a major building block used to enable these systems to function under non-ideal environments.
The Soft-Decision Forward Error Correction (SD-FEC) integrated block supports Low Density Parity Check (LDPC) decoding and encoding and Turbo code decoding. The LDPC codes used are highly configurable, and the specific code used can be specified on a codeword-by-codeword basis.
Soft-Decision FEC Integrated Block
Overview
Key Features
- Function configurable between either:
- LDPC decode or encode of a range of customer specified Quasi-cyclic (QC) codes, or
- Turbo decode of codes used by LTE
- Peak throughput of the order:
- 1.78 Gb/s Turbo decode @ 6 iterations
- 3.03 Gb/s for LDPC Decode @ 8 iterations
- 20.34 Gb/s for LDPC Encode
- Scalable implementation
- Multiple instantiations on a device (not all cores supported simultaneously in LDPC and Turbo modes)
- High bandwidth AXI4-Stream interfaces
- Support for customer programming of class of LDPC code
- Significant FPGA resource savings compared to a soft IP implementation
- Overall reduced system power with up to 2x the performance
- Dynamically optimize and configure parameters for evolving 5G standards
Technical Specifications
Related IPs
- Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe)
- Virtex-6 Integrated Block for PCI Express (PCIe)
- Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
- 7 Series Gen2 Integrated Block for PCI Express (PCIe)
- UltraScale Gen3 Integrated Block for PCI Express (PCIe)
- 7 Series Integrated Block for PCI Express (PCIe)