SMIC 65nm LL LPDDR interface for mobile-DDR application

Key Features

  • LPDDR interface for mobile-DDR application;
  • Cell Size (Width * height) 35um * 174um with DUP stagger bonding pads;
  • Work voltage: 1.8V power;
  • Support MDDR, datarate up to 400Mbps;
    • Programmable driven-strength, pull-up/down resistor and Schmitt-trigger control;
  • SMIC 0.065?m Logic 1P10M Salicide 1.2V/2.5V low leakage Process;
    • Suitable for 7, 8, 9 and 10 layers application (double top metal);

Technical Specifications

Foundry, Node
SMIC 65nm LL
Maturity
In Production
SMIC
In Production: 65nm LL
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Semiconductor IP