SMIC 0.13um General Process, 1.2V/2.5V Standard I/O Library
Overview
VeriSilicon SMIC 0.13um 1.2V/2.5V I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um 1.2V/2.5V process. This library can take 3.3V tolerance. This library supports both Stagger I/O pads and Inline I/O pads. They are configurable and variable driving strength between 2mA - 24mA.
Key Features
- VeriSilicon SMIC 0.13um 1.2V/2.5V I/O Cell Library supports design with six, seven or eight layers of metal.
Deliverables
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
Technical Specifications
Foundry, Node
SMIC 0.13um
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV
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