Small footprint, low power, Power on Reset for Silterra CL180G

Overview

Power on Reset IP is designed to generate global reset signal depending on 3.3V Power Supply. The output nReset is low while vcc33 is detected lower than Vth_vcc33_up, the upper threshold of comparator. Once vcc33 rise higher than Vth_vcc33_up the signal nReset goes high until vcc33 falls lower than Vth_33_dn, the lower threshold of comparator. At initial power on nReset is guaranteed to be held low for dT_nReset_up.

Key Features

Dual 1.8V and 3.3V Power Supply Operation
3.3V voltage detector
Low Power Consumption: 350uW
300mV Hysteresis on comparator
Adjustable delay time via external capacitor
Small area
Silterra 0.18um CMOS Logic Generic process (CL180G)
-40...+70°C operating junction temperature
Stage: Silicon-proven

Benefits

Cheap multi-usage license
Small area
Silicon proven
Ready to supply

Block Diagram

Deliverables

Brief Datasheet
Design models (Verilog, .LIB)
Application Note
GDSII database
Final Hard Macro placement file (.LEF)
DRC Report

Technical Specifications

Foundry, Node

Silterra 0.18um CMOS Logic Generic process (CL180G)

Availability

Available to supply

Silterra

Silicon Proven: 180nm

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