SLVS-EC v3.0 Rx IP is an interface IP core that runs on Altera® FPGAs. Using this IP, you can quickly and easily implement products that support the latest SLVS-EC standard v3.0. You will also receive an "Evaluation kit" for early adoption.
* Altera® FPGAs can receive signals directly from the SLVS-EC Interface.
* Compatible with the latest SLVS-EC Specification Version 3.0.
* Supports powerful De-Skew function. Enables board design without considering Skew that occurs between lanes.
* "Evaluation kit”(see below) is available for speedy evaluation at the actual device level.
SLVS-EC Interface for FPGA
Overview
Key Features
- SLVS-EC Specification Version 1.2/2.0 and the latest 3.0 are supported.
- Provides various functions defined in the SLVS-EC Link Layer.
- Selectable 32 or 64 pixel for output interface
- Supports 8, 10, 12, 14, 16 bit/pixel
- Realizes transfer with less overhead compared to conventional ANSI 8b10b by taking advantage of GCC (Gigabit Channel Coding) features added in the latest SLVS-EC Version 3.0.
- Supports error correction using Error Correction Code (ECC)
- Supports Byte to Pixel conversion in 1, 2, 4, 6, and 8 lane configurations.
- Header analysis and payload error detection.
- Compile options allow removal of unnecessary functions.
Block Diagram
Deliverables
- Encrypted RTL (Verilog HDL)
- Reference design
- Simulation environment (For ModelSim)
- User's manual, reference manual, simulation manual
Technical Specifications
Short description
SLVS-EC Interface for FPGA
Vendor
Vendor Name