The eSi-SP-FP-Int-to-Float IP core implements single-precision (32-bit), IEEE 754 compliant, integer to floating-point conversion.
Single precision, IEEE 754, integer to floating point conversion
Overview
Key Features
- Single-precision (32-bit) integer to floating point conversion.
- IEEE 754 compliant.
- Support for signed and unsigned integers.
- Status flags indicating invalid.
Deliverables
- Verilog RTL
- Testbench
- Simulation and synthesis scripts
- Documentation
Technical Specifications
Maturity
Silicon proven in multiple products
Availability
Immediate
Related IPs
- Single precision, IEEE 754, floating point to integer conversion
- Single precision, IEEE 754, floating point adder
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- Half precision, IEEE 754, floating point fused multiply add