The eSi-SP-FP-Float-to-Int IP core implements single-precision (32-bit), IEEE 754 floating-point to integer conversion.
Single precision, IEEE 754, floating point to integer conversion
Overview
Key Features
- Single-precision (32-bit) floating point to integer conversion.
- IEEE 754 compliant.
- Support for signed and unsigned integers.
- Full support for infinities, NaNs and denormals.
- Status flags indicating invalid and inexact.
Deliverables
- Verilog RTL
- Testbench
- Simulation and synthesis scripts
- Documentation
Technical Specifications
Maturity
Silicon proven in multiple products
Availability
Immediate
Related IPs
- Single precision, IEEE 754, integer to floating point conversion
- Single precision, IEEE 754, floating point adder
- Single precision, IEEE 754, floating point multiplier
- Single precision, IEEE 754, floating point divider
- Single precision, IEEE 754, floating point square root
- Half precision, IEEE 754, floating point fused multiply add