The eSi-SP-FP-Divider IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point division.
Single precision, IEEE 754, floating point divider
Overview
Key Features
- Single-precision (32-bit) floating point division.
- IEEE 754 compliant.
- Full support for infinities, NaNs and denormals.
- Rounding is to the nearest even number.
- Status flags indicating invalid, overflow, underflow, divide by zero and inexact.
- Configurable number of pipeline stages.
- Supports one operation per cycle.
Deliverables
- Verilog RTL
- Testbench
- Simulation and synthesis scripts
- Documentation
Technical Specifications
Maturity
Silicon proven in multiple products
Availability
Immediate
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