Single precision floating-point fast speed parametrized multi operands adder

Overview

Key Features

• Synthesizable, technology independent Verilog HDL Core.
• 32 bits floating-point arithmetic.
• IEEE 754 compliant.
• High-speed fully pipelined architecture.
• Only 7 clock-cycles of latency.
• It can mix of addition and subtraction together.
• Max operands 4, it can be defined 2-4 as you like.

Benefits

• (1).Faster speed,only 7 clock-cycles of latency.
• (2).Parametrized, customers can choose how many operands.

Applications

• Floating-point pipelines and arithmetic units.
• Floating-point processors.

Deliverables

• license

Technical Specifications