Fastest multiplier only two cycles .
less resources occupied.
Single precision floating-point 2 cycle's multiplier
Overview
Key Features
- Synthesizable, technology independent Verilog HDL Core.
- 32 bits floating-point arithmetic.
- IEEE 754 compliant
- High-speed fully pipelined architecture.
- Only 2 clock-cycles of latency.
Benefits
- fastest Multiplier in the world.
- occupies less resources .
Block Diagram
Applications
- Floating-point pipelines and arithmetic units.
- Floating-point processors.
Deliverables
- license
Technical Specifications
Maturity
verified
Availability
ready to market
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