Single Port SRAM compiler - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k

Overview

Key Features

• Available for Free Download and Use
• Reduced die cost
• Up to 15% denser than standard memory compilers
• Pushed rule bit cell from foundry
• Routing allowed upwards from Metal 4, Support Metal 5 top Metal option
• Ultra low dynamic power
• Multi-plane architecture
• Byte write capability
• Flexible power routing: power ring or ring-less
• Low power architecture even at nominal voltage: Up to 50% less consuming than standard memory compilers available at 90 nm LP
• Low voltage capability: for additional 30% power consumption savings when operating at 1.0 V +/-10%
• Ultra low leakage design
• Designed with the latest HVt PRBC from TSMC
• 40% less leaky in stand by mode compared with a standard SpRAM compiler at 90 nm LP
• Optional Data retention mode
• Easy integration
• Mux factor can be chosen
• Wide flexibility for words and bits per word
• The Dolphin quality
• Complete mismatch validation of the memory architecture taking in account local and global dispersion
• Optional BIST for industrial fabrication test of instances

Technical Specifications