Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k

Overview

Foundry sponsored - Single Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and Low power - compiler range up to 640 k

Foundry Sponsored memory generator
Migration on an existing architecture already available for other processes (90, 85, 55 nm)
Configuration
SVT transistors for memory periphery
uHD HVT Pushed rule bit cell from foundry
Designed with 4 metal layers, routing enabled over the memory in metal 5
Smart periphery design to reach the highest density
Up to 10% denser than standard memory generators at 90 nm
Low leakage design
Data retention mode at nominal voltage (1.2 V) and low voltage (0.77 V) for 4x leakage reduction compared to standard stand by mode
Low dynamic power
Partitioned array to reach ultra low power consumption
Variable write-mask capability
Easy integration
MUX options
Data range flexibility allows easy addition of bits for redundancy or ECC purposes
Address range flexibility allows easy addition of single rows for redundancy purposes
The Dolphin quality
Complete mismatch validation of the memory architecture taking in account local and global dispersion
High robustness thanks to self-timing access scheme
Compliance with TSMC IP9000 qualification process

Maturity

In_Production