Single Port SRAM Compiler IP, UMC 40nm LP process
Overview
ULL Single Port SRAM with row redundancy, UMC 40nm LP process.
Technical Specifications
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon:
40nm
LP
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- Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k
- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k