Vendor: Terminus Circuits Pvt Ltd. Category: Single-Protocol PHY

USB 3.1 PHY

USB 3.1 is the most recent version of the USB (Universal Serial Bus) standard for connecting electronic devices in host and devic…

Contact Provider Request Datasheet

Overview

USB 3.1 is the most recent version of the USB (Universal Serial Bus) standard for connecting electronic devices in host and device mode. USB 3.1 IP is targeted for integration into SoCs for media storage, and playback devices requiring faster bandwidth between PCs and portable electronic devices.

The vendor offers best-in-class SerDes IP for USB 3.1 PHY. The PHY is designed for low latency, low power, small form factor, high interface speeds for high performance computing. The PHYs comes complete with a physical media attachment (PMA) hard macro that supports USB 3.0 and USB3.1 protocols, a physical coding sublayer (PCS) and soft macro for USB that is PIPE4.2 compliant.

Key features

  • Parallel data widths of 8bits and 16bits
  • QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
  • Support signal loss and receiver detection using programmable multi-tap & de-emphasis
  • Support 1m cable
  • High speed low jitter (0.17UI) 10GHz PLL

What’s Included?

  • User and integration guides
  • Netlist
  • Timing library
  • Register map
  • Verilog
  • IBIS-AMI models
  • LEF views
  • Layout Versus Schematic (LVS)
  • Design Rule Check (DRC) reports
  • Silicon

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
USB 3.1 PHY
Vendor
Terminus Circuits Pvt Ltd.

Provider

Terminus Circuits Pvt Ltd.
HQ: Bangalore- 560094, India
Terminus Circuits offers High Speed Serial Link Interface IPs and provide interconnect solutions across many standards like USB.org, PCIe-SIG, MIPI Alliance, IEEE, SATA, VESA etc. These transceivers are an integral part of any HPC systems providing interconnect solutions that scale bandwidth and deliver end-to-end signal integrity in next-generation platforms. The architecture for these IPs are modular and scalable to meet the requirements of next generation SoCs, ASICs, NoCs, NPUs for high performance computing. These robust PHY IPs are available for different foundries and broad spectrum of process technology nodes. Terminus Circuits have flexible business models - Licensing / Integration / Joint IP Development, to help customers reduce time-to-market.
Contact Terminus Circuits Pvt Ltd.

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is USB 3.1 PHY?

USB 3.1 PHY is a Single-Protocol PHY IP core from Terminus Circuits Pvt Ltd. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP